This application claims the priority of Korean Patent Application No. 2002-54257, filed Sep. 9, 2002 in the Korean Intellectual Property Office (KIPO), which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method of increasing efficiency of redundancy repair of a semiconductor memory device having a plurality of memory banks.
2. Description of the Related Art
In general, several redundancy memory cells are included in each memory bank in a semiconductor memory device with a multi-bank structure in which a plurality of memory banks are arranged. Defective memory cells are repaired in units of memory banks. That is, when a defective memory cell is included in a memory bank, this cell is replaced with a redundancy memory cell in the memory bank. However, if no redundancy memory cell is present in the memory bank, the defective memory cell cannot be repaired.
In a conventional semiconductor memory device, the respective memory banks include redundancy memory cells of the same numbers.
FIG. 1 is a diagram of an example of a semiconductor wafer in which a plurality of semiconductor memory devices 100 with conventional redundancy schemes are aligned. In general, a semiconductor wafer consists of a plurality of semiconductor memory devices 100. In FIG. 1, the semiconductor wafer is illustrated to have four semiconductor memory devices 100.
It is assumed that the semiconductor wafer of FIG. 1 uses four die masks per photo shot, i.e., a photo shot process is performed on the semiconductor wafer in units of four semiconductor memory devices. In the photo shot process, a semiconductor wafer, which is coated with a photo resist, is covered with a photo mask of a designed circuit pattern, and exposure and development processes are performed on the semiconductor wafer using a photographic imaging apparatus.
Each semiconductor memory device 100 includes a plurality of memory blocks 110 and each memory block 110 includes sixteen memory banks. Although not illustrated in detail, each memory bank has normal memory cells, and a redundancy memory cell. When a normal memory cell has defects, this cell is replaced with a redundant memory cell.
The conventional semiconductor memory device 100 is designed to have the same redundancy scheme in each memory bank 110, so that the number of redundant memory cells, redundant rows, or redundant columns is set to be the same in each memory bank 110. However, repair rate of defective memory cells in a memory bank at an edge portion of a photo shot is higher because a photo margin is insufficient in the photo shot process.
In a conventional redundancy scheme in which each memory bank has redundant memory cells of the same numbers, defective memory cells cannot be effectively repaired in the case where the number of defective memory cells included in each memory bank is different in manufacture of a semiconductor wafer. For instance, many redundant memory cells in a memory bank having less defective memory cells are left after the repair of the defective memory cells, whereas redundant memory cells in a memory bank having more defective memory cells are not ample for the repair of the defective memory cells and many defective memory cells are not repaired.
Referring to FIG. 1, a photo shot process is performed on the semiconductor wafer of FIG. 1 in units of four semiconductor memory devices. During the photo shot process, a rate of defective memory cells in memory banks 130 at edges of a photo shot is higher, thereby reducing yield, that is, the ratio of good-quality semiconductor memory devices with respect to the overall semiconductor memory device. However, if the number of redundant memory cells of each memory bank is increased in order to raise the yield, the size of a semiconductor chip is increased.